Rambus Provides PCIe 6.0 Interface Subsystem for High-Performance Data Centers and IA SoCs | Company

SAN JOSE, Calif.–(BUSINESS WIRE)–October 24, 2022–

Rambus Inc. (NASDAQ: RMBS), a leading provider of chip and silicon IP that makes data faster and more secure, today announced the availability of its PCI Express® interface subsystem (PCIe®) 6.0 consisting of PHY and controller IP. The Rambus PCIe Express 6.0 PHY also supports the latest version of the Compute Express Link™ (CXL™) specification, version 3.0.

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PCIe 6.0 interface subsystem (Graphic: Rambus Inc.)

“The rapid evolution of AI/ML and data-intensive workloads drives the continued evolution of data center architectures requiring ever higher levels of performance,” said Scott Houghton, General Manager of Interface. IP at Rambus. “The Rambus PCIe 6.0 interface subsystem supports the performance demands of next-generation data centers with class-leading latency, power, area, and security.”

The Rambus PCIe 6.0 interface subsystem offers data rates of up to 64 gigatransfers per second (GT/s) and has been fully optimized to meet the needs of advanced heterogeneous computing architectures. Within the subsystem, the PCIe controller has a Data Integrity and Encryption Engine (IDE) dedicated to protecting the PCIe links and the valuable data transferred over them. On the PHY side, full CXL 3.0 support is available to enable chip-level solutions for cache-coherent memory sharing, expansion, and pooling.

“PCIe is ubiquitous in the data center and CXL will become increasingly important as enterprises seek ever-increasing speeds and bandwidths to support higher levels of performance in next-generation applications,” said Shane Rau, research vice president, Computing Semiconductors at IDC. “As an increasing number of chip companies emerge to support new data center architectures, access to high-performance interface IP solutions will be critical to enabling the ecosystem.”

Key features of the Rambus PCIe 6.0 interface subsystem include:

  • Supports PCIe 6.0 specification, including 64 GT/s data rate and PAM4 signaling
  • Implements low-latency forward error correction (FEC) for link robustness
  • Supports fixed-size FLITs that enable high bandwidth efficiency
  • Backwards compatible with PCIe 5.0, 4.0 and 3.0/3.1
  • State-of-the-art security with an IDE engine (controller)
  • Supports CXL 3.0 for new usage patterns that optimize memory (PHY) resources

More information:

For more information on the PCIe 6.0 interface subsystem, visit rambus.com/interface-ip/serdes/pcie6-phy/.

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About Rambus Inc.

Rambus is a provider of cutting-edge chips and silicon IP that makes data faster and more secure. With over 30 years of experience in advanced semiconductors, we pioneer high-performance memory subsystems that solve the bottleneck between memory and processing for data-intensive systems. Whether in the cloud, at the edge, or in your hand, real-time and immersive applications depend on data throughput and integrity. Rambus products and innovations provide the increased bandwidth, capacity and security needed to meet global data needs and deliver ever better user experiences. For more information, visit rambus.com.

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CONTACT: Cori Pasinetti

Rambus Corporate Communication

Phone. : (650) 309-6226

[email protected]

KEYWORD: UNITED STATES NORTH AMERICA CALIFORNIA

INDUSTRY KEYWORD: SOLID STATE DATA MANAGEMENT TECHNOLOGY ARTIFICIAL INTELLIGENCE HARDWARE INTERNET

SOURCE: Rambus Inc.

Copyright BusinessWire 2022.

PUBLISHED: 10/24/2022 5:00 PM / DISK: 10/24/2022 5:02 PM

http://www.businesswire.com/news/home/20221024005307/en

Copyright BusinessWire 2022.