Enhanced Serial Peripheral Interface (eSPI) Master/Slave Controller – EEJournal

DCD-SEMI, a leading IP Core vendor and SoC design house from Poland, has mastered the unique DeSPI IP Core. It is a fully configurable eSPI Master/Slave device supporting all features described in the Enhanced Serial Peripheral Interface Base Specification rev. 1.0. The DESPI master should be used by the microcontroller to communicate with eSPI devices. The DESPI slave should be used as an eSPI device, for example, an embedded controller connected to the Intel CPU system.

Bytom, Poland on June 28, 2022. The eSPI bus is an enhancement of the LPC bus. The serial clock line (_sck) synchronizes the shifting and sampling information on the IO lines. – It is a technology independent design that can be implemented in a variety of process technologies – explains Jacek Hanke, CEO of DCD-SEMI.

DESPI is flexible enough to interface directly with many devices. The system can be configured as either a master or a slave, and depending on the master configuration either the _in or _out lines will be used. Its serial clock can run up to 66 MHz – adds Hanke.

DESPI is also capable of single, dual and quadruple SPI transfers. The DESPI is fully customizable, meaning it comes in the exact configuration with the target design requirements. Additionally, the DESPI module is equipped with receiver and transmitter FIFOs, capable of storing up to 4096 + 16 bytes (header and maximum data payload) in separate buffers for each eSPI channel. (Displayed and undisplayed peripheral channel, virtual wired channel, out-of-band channel, flash access channel).

Additionally, customizable peripheral channel memory and IO port, Virtual Wire lines and event lines are also supported. An interesting and unique feature is the alert mechanism, used by the eSPI slave to request a service from the eSPI master.

The controller is able to operate in several eSPI configurations:

  • Unique Master – Unique Slave,
  • Single master – Multiple slaves.

DCD SPI cores are part of our growing family of peripherals which also includes protocols such as I3C and IR. DCD SPI cores have been successfully implemented in embedded microprocessor boards, consumer and professional audio/video, home and automotive radio, low-power mobile applications, communication systems, and digital multimeters.

More information: https://www.dcd-semi.com/product/despi/

About DCD-SEMI

DCD-SEMI has two decades of experience in the IP market. The company was founded in 1999 in Bytom, Poland, and masters more than 70 different architectures, including the world’s fastest 8051 processor, a royalty-free and fully upgradeable 32-bit processor, and a 100% cryptographic system. Automotive IP cores designed by DCD-SEMI are offered as a CAN ALL package – a bespoke IP core that has been successfully implemented by dozens of automotive companies such as VW, Toyota and now GuardKnox. More information can be found at: www.dcd-semi.com, www.cfdsemi.com and www.crypt-one.com.