Automate memory testing via a shared bus interface

The use of memory-intensive IPs in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-intensive IPs often only have one access point to test the memories. A shared bus architecture allows testing and repair of memories in IP cores through a single access point called a shared bus interface. In this interface, designers need design-for-test (DFT) tools to automatically connect to DFT signals to apply memory BIST models.

In addition to automating DFT, Siemens Digital Industries Software also offers an automated approach called shared bus learning to map the physical memory composition of each logic memory and validate cluster and logic memory library files.

Why use a shared bus architecture

Current designs contain many memory arrays and consume a substantial portion of the total chip area. This increase in memory size and count incurs additional hardware cost for the associated memory built-in self-test (MBIST) logic. Therefore, the MBIST logic area and additional routing requirements can negatively impact chip performance in critical functional paths to and from memories.

A shared bus architecture provides a common access point for multiple memories, allowing designers to optimize core routing and performance. It also provides the flexibility to route DFT signals along functional paths behind the shared bus interface. Figure 1 illustrates a shared bus architecture containing a memory array module that provides access to multiple memories.

Fig. 1: Shared bus cluster in one chip.

The memories accessible via the shared bus interface are called logic memories (LM_0 to LM_4 in Figure 1). These logic memories can be inside or outside of a cluster module. A logical memory address space is made up of one or more physical memories (PM_* in Figure 1).

BIST memory shared bus hardware

The built-in test hardware generated for the shared bus includes an MBIST controller, memory interfaces, and additional modules such as virtual memories and glue logic. The MBIST shared bus hardware is shown in Figure 2.

Fig. 2: BIST memory shared bus hardware.

One dedicated MBIST controller is assigned per shared bus memory cluster module. Virtual memories correspond to logical or physical memories inside the shared-bus memory array module. Tessent MemoryBIST automatically generates virtual memory consisting only of threads and feedthroughs to mimic memory behavior. Binding logic controls access between shared bus interface ports, the MBIST controller, and virtual memories. Virtual access allows the MBIST controller to run memory algorithms and perform standard operations on any logical or physical memory.

All BIST memory shared bus hardware is packaged in a wrapper module. Wrapping allows optimization of the cross-border area during synthesis and reduces unbundled logic in the design after synthesis. This methodology improves logical optimization and reduces surface area.

Shared Bus DFT Flow Automation

Tessent MemoryBIST provides an automated solution that supports memory library file mapping and validation, memory repair, complex memory configurations, and several ways to optimize the area.

A unique feature of the tool is the ability to automate the mapping of the physical memory composition of each logical memory and validate cluster library and logical memory files. This so-called shared-bus learning flow is shown in Figure 3.

Fig. 3: Overview of shared bus learning flow. TCD is the basic description of Tessent.

Shared Bus Learning involves two key features:

  • Physical-to-logic (P2L) mapping automation
  • Library Validation

P2L mapping creates wrappers by first deriving physical memory mappings into logical memory from the RTL memory cluster. Then it fills the extracted information into the logical memory library file, also called TCD (Tessent Core Description); and finally, it writes the updated files.

Library validation verifies that:

  • No memory is omitted from MBIST tests
  • The port mappings specified in the cluster and TCD logical memory are consistent with the design
  • The pipeline steps that surround the logical memory are consistent with the TCD cluster

Serviceable memories in a memory array module

Tessent MemoryBIST supports repairable memories with Line/Word only, Column/I/O only, and Line/Column repair types in a shared bus cluster by inserting Built-in Repair Analysis (BIRA) and auto- Integrated Repair (BISR) required. ) logic, as shown in Figure 4.

Fig. 4: Overview of memory array module design with BISR.

Complex memory configurations: multi-port and pseudo-vertical stacking

Tessent MemoryBIST supports testing of multiport memories within the shared bus memory cluster. It allows you to detect inter-port faults and provides the flexibility to control concurrent read/write operations. The MBIST DFT insertion stream for multi-port memories is the same as for single-port memories.

Tessent also supports some complex memory configurations where the physical memories are larger than the logical memory. The concept of slicing larger physical memory to fit a smaller logical memory footprint is called pseudo-vertical stacking.

Area optimization in DFT shared bus

Test MemoryBIST minimizes shared bus test logic area by automatically reusing memory interface logic. If identical memories in design are not tested simultaneously, then the memory interface and virtual memory are reused among identical memories. Similarly, repair sharing can be implemented on memories with Line/Word only, Column/I/O only, and Line/Column repair types. Memories of different sizes can share the same BISR/BIRA hardware. Repair sharing applies the same repair information to all memories in a repair group. The designer also has control over the level of memory sharing or pooling on a BISR/BIRA circuit to maintain a proper balance between potential performance impact and improvements in area and turn-on time.

With shared bus architectures becoming increasingly important, designers now have reliable automation to simplify even the most difficult DFT tasks. Tessent MemoryBIST efficiently addresses the ever-increasing demand for testing complex memory configurations with automated support for memory library mapping and validation, DFT insertion, and DFT area optimization.

Harshita Kodali

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Harshitha Kodali is a Product Engineer for the Tessent Group at Siemens Digital Industries Software.